IMPAC: Getting more for less: Innovative MPSoC Architecture Paradigms for Analysability and Composability of Timing and Power

DATE 2016 Friday Workshop, March 18th, 2016, Dresden


Presentation slides now available for download.

Today’s MPSoCs cannot only potentially provide high performance but also the possibility of integrating more than one application. With more than one application, different workload demands need to be handled like strict timing for safety critical real-time applications or best-effort computation for, e.g., video processing. Ensuring dependable behaviour of such systems with respect to timing and power is a huge challenge for state-of-the-art analysis methods. Without support from the hardware platform, firmware and software, this analysis can become extremely cumbersome. Furthermore, the independent analysis and incremental integration of different applications on a single chip becomes infeasible.

To support the analysability of MPSoCs, predictable and composable architectures with appropriate software layer support have been proposed. This ranges from less-predictable best effort (Average Case Analysis) over cycle-level predictable (Static Timing Analysis) to predictable and randomized (Probabilistic Timing Analysis) MPSoC platforms.

This workshop aims at presenting and discussing the latest research results within this spectrum of topics, with emphasis on new on-chip architectures and analysis paradigms to enable fast, yet accurate, and dependable analysis, to support the incremental integration of heterogeneous applications in MPSoCs.  The workshop, whose presentations are by invitation only, will bring together representatives of the major European projects in the field as well as academic/industrialist experts on the field. The workshop audience will be exposed to the latest developments, at hardware and software level, on predictable and composable platforms.



Dr. Francisco J. Cazorla, BSC, Spain

Dr.-Ing. Ralph Görgen, OFFIS, Germany

Prof. Dr. Roman Obermaisser, University of Siegen, Germany


Workshop Material and Presentation Slides:

Workshop Flyer

Addressing the Path Coverage Problem with Measurement-based Timing Analysis - Tullio Vardanega (University of Padova )

Analysis of Power – Measurement, Simulation, and Composability - Kim Grüttner (OFFIS)

DREAMS: Dependable NoC - Hamidreza Ahmadian (University of Siegen)

Model-Based Code Generation for the MPPA Manycore Processor - Benoît Dupont de Dinechin (Kalray)

Safe and Secure Real-Time (SSRT) - Benjamin Gittins (Synaptic Labs)

PROXIMA Probabilistic Architecture for FPGA and COTS - Francisco Cazorla (BSC)

CompSOC: A Predictable and Composable Multicore System - Kees Goossens (TU/e)